Home > Servers > Rack and Tower Servers > Intel > White Papers > Memory Population Rules for Intel® Xeon® Scalable Processors on PowerEdge Servers > Memory topography and terminology
To understand the relationship between the CPU and memory, terminology illustrated in Figure 1 must first be addressed:
Memory channels are the physical layer on which the data travels between the CPU and memory modules. Channels were intended to be populated in a symmetrical fashion, so that when two channels horizontal to one another are populated, an interleave set will be created. Xeon® processors have eight memory channels.
Processor | Channel | Channel | Channel | Channel | Channel | Channel | Channel | Channel |
Slots for Processor 1: | A1 and A9 | A7 and A15 | A3 and A11 | A5 and A13 | A4 and A12 | A6 and A14 | A2 and A10 | A8 andA16 |
Slots for Processor 2: | B1 and B9 | B7 and B15 | B3 and B11 | B5 and B13 | B4 and B12 | B6 and B14 | B2 and B10 | B8 and B16 |
For this quad CPU design, populate the memory in round robin order, starting with CPU1, then CPU2, CPU3 and CPU4. Optimized population order is:
A1,B1,C1,D1,A2,B2,C2,D2,A3,B3,C3,D3, and so on.