Home > Servers > PowerEdge Components > White Papers > Memory Population Rules for 3rd Generation Intel Xeon Scalable Processors on PowerEdge Servers > Overview
Understanding the relationship between a server processor (CPU) and its memory subsystem is critical when optimizing overall server performance. Every processor generation has a unique architecture, with volatile controllers, lanes and slot population guidelines, that must be satisfied to attain high memory bandwidth and low memory access latency.
Dell EMC PowerEdge products with 3rd Generation Intel Xeon Scalable Processors now offer a total of eight memory channels with up to two memory slots per channel; a total of sixteen memory modules per processor. This presents numerous possible permutations for configuring the memory subsystem with traditional Dual In-Line Memory Modules (DIMMs) and Optane DC Persistent Memory Modules (DCPMMs), yet there are only a couple of balanced configurations that will achieve the peak memory performance that Dell EMC PowerEdge servers can deliver.
Memory that has been incorrectly populated is referred to as an unbalanced configuration. From a functionality standpoint, an unbalanced configuration will operate adequately, but introduces significant additional overhead that will slow down data transfer speeds. Similarly, a near balanced configuration does not yield fully optimized data transfer speeds but it is only suboptimal to that of a balanced configuration.
Conversely, memory that has been correctly populated is referred to as a balanced configuration and will secure optimal functionality and data transfer speeds.
This white paper explains how to balance both traditional DIMMs and DCPMMs configured for 3rd Generation Intel® Xeon® Scalable Processors with Dell EMC PowerEdge servers.