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During the back-end design phases, the data access pattern becomes more sequential. Some of the physical design implementation workflows for block level design tends to have a smaller number of jobs with a sequential I/O pattern that run for a very long period of time. The output of all the jobs involved in a chip's design phases can produce terabytes of data. Even though the output is often considered transient, and placed on scratch space, the data still requires the highest tier of storage for performance. Within the storage system, workflows tend to store a large number of files in a single directory, typically per design phase, amid a deep directory structure on a large storage system. The performance-sensitive project directories, including those for both scratch and non-scratch directories, dominate the file system and can become a bottleneck for legacy, scale-up storage solutions.
The directories contain source code trees, RTL files that define logic in Hardware Description Language (HDL), binary compiled files after synthesis against foundry libraries, and the output of functional verifications and other simulations. Typically, the RTL project directories that contain source code are minimal in size, while the project directories used for simulations dominate the overall capacity utilization of the storage system.