Home > Storage > PowerScale (Isilon) > Industry Solutions and Verticals > Electronic Design Automation > PowerScale: Best Practices for Semiconductor EDA Design Environments > Advanced tuning
The settings in this section should be modified in consultation with an SE as well as support personnel. EDA workloads can be varied in nature from front-end and back-end by chip design, various EDA tools used for chip design so every tunable may not be applicable to each scenario.